Flagship Product

ChipNexus — SoC DocFlow

AI-powered automated SoC Reference Manual generation. From 6–8 weeks to under 4 hours. Zero parameter errors. Single-source publishing.

Proven Results at Scale
270×
Faster RM Generation
100%
Parameter Accuracy
0
Manual Entry Errors
−40%
Support Queries via AI Chatbot
80%
Fewer Build Failures
40+
Active Users Worldwide
50+
Reference Manuals Generated
95%
IP Spec Reuse Across SoCs
How It Works
7-Step Automated Pipeline
From RTL design elaboration to published documentation — fully automated, single source of truth, with AI-assisted content generation and human oversight.
1
RTL Elaboration
RTL Design Elaboration parses SV/VHDL, extracts parameters
2
Memory Map
XLSX→IMAP with addresses & overrides
3
Non-RTL DB
JSON-based parameter enrichment
4
DITA Auto-Gen
Claude API generates chapters
5
DITA-OT Resolve
Parameter resolution + SVG diagrams
6
RAG Ingest
Vector KB for AI chatbot
7
Publish
PDF + WebHelp + Chatbot KB
Architecture
7 Subsystems, 1 Unified Platform
VS Code Extension (Unified UI)
Design Analysis
RTL Design Elaboration
IMAP Generator
Memory Map→XML
Non-RTL DB
JSON Ditabase
DITA Generator
Claude API
RM Explorer
Flask + RAG
Output: SVG Diagrams + Resolved DITA + PDF + WebHelp + RAG KB
Core Subsystems
🖥️
VS Code Extension
One-click design analysis, parameter explorer, build pipeline WebView, DITA preview, and RM Explorer launcher — all within VS Code.
🔬
RTL Design Elaboration Elaboration
Full SystemVerilog/VHDL design elaboration extracting all parameters with hierarchical resolution, type tracking, and source line references.
🗺️
IMAP Generator
Converts architecture team Excel memory maps into structured XML Instance Map files with automatic parameter merging and address validation.
🗄️
Non-RTL Parameter DB
Git-versioned JSON database for documentation-specific parameters. CI-integrated gap analysis, contribution YAML workflow, schema validation.
🤖
AI Chapter Generation
Claude API extracts SoC-specific chapters (clocking, reset, interrupts, power) from architecture PDFs. AI extracts, humans verify, pipeline includes.
📐
Register Diagram Renderer
Custom DITA-OT plugin generating SVG bit-field diagrams with colour-coded access types and multi-instance memory map tables.
💬
RAG Chatbot
Flask-based RM Explorer with RAG-powered AI assistant. Natural language queries with source citations — 40% reduction in support tickets.
File Formats
Custom XML Formats for Semiconductor Documentation
Extended DITA-OT with four custom formats, each with formal XSD schemas hosted at bridgon.com/platform/.
parameter definitions
Parameter Definition
Configurable parameters with defaults, constraints, types. RTL + non-RTL sources.
instance mappings
Instance Map
Per-instance parameter overrides with base addresses and register file references.
register databases
Register Database
IP-XACT-compatible register definitions with bitfields, access types, and encodings.
publishing configs
Publishing Instructions
Resolution groups, merging rules, output targets, parameter ordering.
Platform Documentation
XSD Schemas at bridgon.com/platform/
All custom file formats have formal XSD schemas served from our domain for XML validation.
http://bridgon.com/platform/param-mapping    ← bridgon-docs
http://bridgon.com/platform/instance-map     ← bridgon-docs
http://bridgon.com/platform/register-db      ← bridgon-docs
http://bridgon.com/platform/publishing       ← bridgon-docs

An OASIS XML Catalog (catalog.xml) maps all namespace URIs to local XSD files. Standard DITA-OT DTDs are delegated to the bundled DITA-OT 4.4 distribution.

Open Source
Deploy ChipNexus in Your Organization
Modular architecture with swappable components. Swap RTL Design Elaboration for Open-Source Elaboration, DITA-OT for Sphinx, Claude for GPT-4 — all without architectural changes.
Talk to Our Team →